1. Field of the Invention
The present invention relates to a method for manufacturing storage electrodes in a semiconductor memory device and a structure of those storage electrodes, and more particularly to a structure and method for manufacturing storage electrodes of dummy cells arranged at the peripheral portion of a cell region in a semiconductor memory device.
2. Description of the Prior Art
Semiconductor memory devices are mainly classified into products of a random access memory (RAM) type having a data volatility and products of a read only memory (ROM) type having no data volatility. In the case of a semiconductor memory device, which is of the RAM type and includes one access transistor and one capacitor, as in a dynamic RAM (DRAM), the data storing ability depends on the capacitance of the capacitor. For this reason, if such a semiconductor memory device has an insufficient capacitance, it may involve data errors. That is, data previously stored in the semiconductor memory device may be erroneously read out. In order to avoid such data errors in such a semiconductor memory device, it is necessary to periodically conduct a refresh operation adapted to store again the previously stored data after a predetermined period of time elapses. An increase in capacitance may improve refresh characteristics since the refresh operation is effected by the capacitance. However, this is impractical for recently developed high density semiconductor memory devices having reduced unit cell area. Such a reduction in the unit cell area decreases in the area where a capacitor is formed.
Generally, capacitance is proportional to the surface area where a storage electrode serving as a lower electrode and a plate electrode serving as an upper electrode are in spaced relation with each other while being inversely proportional to the distance between those two electrodes. In order to form a storage electrode having a surface area as large as possible within a limited area on the chip, a method has been proposed in which a capacitor under bit-line (CUB) structure formed with a capacitor under a bit line is also formed with a capacitor over the bit line using a capacitor over bit-line (COB) process, so that a stacked capacitor having a three-dimensional structure, such as a cylindrical, box, or pin type, is manufactured.
FIG. 1 is a schematic plan view illustrating a typical semiconductor device. As shown in FIG. 1, the semiconductor device includes a plurality of cell regions divided from one another by a peripheral circuit region. In FIG. 1, the reference character xe2x80x9cAxe2x80x9d denotes a boundary area between one cell region and the peripheral circuit region. In such boundary areas, diverse dummy patterns, such as dummy gates, dummy bit lines, and dummy capacitors, are typically formed. Although such dummy patterns are not associated with practical operations, they are provided to ensure the reliability of main cells and to achieve an improvement in resolution in a photolithography process. In recently developed semiconductor memory devices having storage electrodes with an increased height, thereby obtaining a higher capacitance with greater packing density, the increased height of those storage electrodes may cause a problem in that the storage electrode patterns of dummy cells arranged in the boundary area xe2x80x9cAxe2x80x9d, between the cell region and peripheral circuit region, are smaller than a desired size due to a loading effect produced during formation thereof that may them to collapse. Where the storage electrode patterns collapse, a bridge phenomenon occurs, which results in a short circuit between adjacent storage electrodes. In order to solve this problem, a method has also been proposed in which the storage electrodes of dummy cells are connected together to form a single pattern.
FIG. 2 is a schematic enlarged plan view corresponding to the portion xe2x80x9cAxe2x80x9d of FIG. 1.
Referring to FIG. 2, a cell region typically includes main cells and dummy cells. The dummy cells are arranged at the peripheral portion of the cell region in order to ensure the reliability of the main cells. Respective storage electrodes of the dummy cells are connected together in a bit line direction (the horizontal direction in FIG. 2) and in a word line direction (the vertical direction in FIG. 2) so that they form a single large pattern. In detail, the storage electrodes in each of two dummy cell lines extending in the bit line direction are connected together, whereas the storage electrodes of one dummy cell line extending in the word line direction are connected together.
FIG. 3 is a layout diagram corresponding to FIG. 2.
Referring to FIG. 3, a semiconductor substrate (not shown), which is included in a semiconductor device defined with cell regions and a peripheral circuit region while having main cells and dummy cells at each cell region, is defined with an active region 11 at a desired portion thereof, and a field region (not shown) at the remaining portion thereof. A plurality of uniformly spaced word lines 14 are formed on the substrate in such a fashion that they extend vertically. A plurality of uniformly spaced bit lines 21 are also formed on the substrate in such a fashion that they extend in perpendicular to the word lines 14.
Landing pads 18 are formed at desired portions of active region 11, that is, common drain regions, between adjacent ones of word lines 14 so that they provide direct contacts DC adapted to electrically connect those common drain regions to associated ones of bit lines 21. At respective portions of active region 11 corresponding to source regions, landing pads 18 are also formed between adjacent ones of word lines 14 so that they provide buried contacts BC adapted to electrically connect those source regions to respective storage electrodes 24 of capacitors formed on the substrate. Storage electrodes 24 are provided for the main cells and dummy cells of the semiconductor device, respectively. Storage electrodes 24 of the dummy cells extending in two lines in the bit line direction while extending in one line in the word line direction are connected together in the form of a single pattern. On the other hand, storage electrodes 24 of the main cells are arranged in a matrix array and connected to buried contacts BC, respectively.
FIG. 4 is a cross-sectional view taken along a line B-Bxe2x80x2 of FIG. 3, that is, the bit line direction. FIG. 5 is a cross-sectional view taken along a line C-Cxe2x80x2 of FIG. 3, that is, the word line direction.
Referring to FIGS. 3 to 5, a semiconductor substrate 10, which has main cell regions and dummy cell regions, is first prepared and then defined with an active region 11 and a field region. A field oxide film 12 is then formed on the field region of semiconductor substrate 10. Access transistors, each of which includes a word line 14 and a spacer insulating film 16, are also formed on active region 11 of semiconductor substrate 10. A landing pad 18 is arranged on a desired portion of each access transistor, that is, a source region 17. Landing pad 18 is formed by etching a first interlayer insulating film 20 formed over semiconductor substrate 10, after the formation of the access transistors, in such a fashion that the associated source region 17 is exposed, and then filling an appropriate landing pad material on the exposed source region 17. Storage electrodes 24 for respective dummy cells are arranged in the form of a single pattern on respective landing pads 18 for the access transistors of those dummy cells. Storage electrodes 24 are formed by etching a second interlayer insulating film 22, formed over the structure obtained after the formation of landing pads 18, in such a fashion that the associated landing pads 18 are exposed, and then filling an appropriate storage electrode material on the exposed landing pads 18. Storage electrodes 24 are not separated from one another, but connected together in the form of a single pattern so that a plurality of access transistors share the single storage electrode pattern with one another. As shown in FIG. 5, bit lines 21 are arranged in second interlayer insulating film 22 in a buried fashion.
Storage electrodes 24, for respective main cells, are also formed in the form of a matrix array on respective buried contacts BC in desired portions of active region 11, that is, source regions 17.
Generally, as a semiconductor device has an increased packing density, its pattern for memory cells is gradually reduced in size. In this case, it is difficult to form a pattern having a uniform size throughout the entire portion thereof. In other words, during a photolithography process conducted to form a pattern for memory cells having a reduced size, a particular portion of the pattern may have a size smaller or larger than that of the remaining pattern portion. Such an effect is called a xe2x80x9cloading effectxe2x80x9d. Due to the loading effect, the storage electrodes of dummy cells arranged at the peripheral portion of each cell region may collapse, thereby causing adjacent ones of those storage electrodes to be bridged. In most cases, such a loading effect is frequently generated at the peripheral portions of the cell regions. The formation of the storages electrodes 24 for respective dummy cells in the form of a single pattern results in a great decrease in the above mentioned loading effect. Accordingly, it is possible to eliminate the problem associated with the bridge between adjacent storage electrodes.
In this case, however, another problem may often occur in that the bit lines may be electrically short-circuited with buried contacts BC. Where an electrical short circuit occurs between a bit line and an associated buried contact, the bit line becomes connected with all the storage electrodes of respective dummy cells formed in a single pattern, so that its loading capacitance is excessively increased. This results soft errors occurring during a sensing operation for reading out data.
Therefore, a feature of the invention is to provide a method for manufacturing storage electrodes of a semiconductor memory device, which is capable of eliminating a bridge between adjacent storage electrodes due to a collapse of storage electrodes for dummy cells arranged at the peripheral portion of each cell region in the semiconductor memory device, and a structure of those storage electrodes.
Another feature of the invention is to provide a method for manufacturing storage electrodes of a semiconductor memory device, which is capable of minimizing the loading capacitance generated at respective bit lines of dummy cells, and a structure of those storage electrodes.
Another feature of the invention is to provide a storage electrode structure for a semiconductor memory device capable of preventing soft errors from being generated during a data sensing operation.
In accordance with one aspect, the present invention provides a method for manufacturing capacitor storage electrodes in a semiconductor memory device having main cells and dummy cells located in a cell region the method, comprising forming access transistors on a semiconductor substrate and thereafter depositing an interlayer insulating film, for planarization, over the semiconductor substrate; selectively etching the interlayer insulating film to form holes adapted to selectively expose impurity diffused regions of the access transistors, and thereafter depositing a conductive film, to serve as storage electrodes of capacitors, over the conductive film after forming the holes; and patterning the conductive film to form a plurality of separate storage electrodes so that at least two adjacent dummy cells share a storage electrode.
In accordance with another aspect, the present invention provides a semiconductor memory device having a main cell region and a dummy cell region at a cell region thereof comprising a semiconductor substrate; a plurality of uniformly spaced word lines arranged on the semiconductor substrate; a plurality of uniformly spaced bit lines arranged on the semiconductor substrate that extend in perpendicular to the word lines; direct contacts respectively arranged between adjacent ones of the word lines at active regions defined on the semiconductor substrate and adapted to connect the active regions to associated ones of the bit lines; buried contacts respectively arranged between adjacent ones of the word lines at the active regions and adapted to connect the active regions to associated ones of storage electrodes of capacitors; a plurality of separate dummy storage electrode patterns arranged in the dummy cell region and adapted to form dummy ones of the storage electrodes, each of the dummy storage electrode patterns serving to connect together at least two of the buried contacts arranged adjacent to each other in a word line direction in the dummy cell region; and a plurality of separate main storage electrode patterns arranged in the main cell region and adapted to form main ones of the storage electrodes, the main storage electrode patterns being arranged in a matrix array such that each is connected to an associated one of the buried contacts arranged in the main cell region.
The invention, though, is pointed out with particularity by the appended claims.